1. Field
Embodiments of the present disclosure relate to a semiconductor device, and more particularly, to a memory device including multi-level memory cells.
2. Description of the Related Art
A conventional DRAM includes a memory cell having a capacitor, and stores data while charging or discharging the memory cell. However, the DRAM is a volatile memory due to a leakage current of the capacitor. In order to address the above issue of the DRAM, nonvolatile memories have been developed. In particular, a phase change memory device including phase change memory cells have been developed.
FIG. 1 schematically illustrates the configuration of a conventional phase change memory device shown in FIG. 4 of US Patent Laid-open Publication No. 2012/0063195. The conventional memory device illustrated in FIG. 1 includes a memory cell 102 and a sense amplifier 410. The memory cell 102 is formed of a resistive material of which the resistance value may be changed according to a temperature or current, and has a different resistance value according to data stored therein.
The sense amplifier 410 compares a cell voltage VCELL, which is applied to a bit line according to a current flowing through the memory cell 102, to a reference voltage VREF(t) that increases with time, and detects the data stored in the memory cell 102.
According to such a structure, however, since the current must be continuously supplied to the memory cell 102 until the sense amplifier 410 detects the data stored in the memory cell 102, power consumption increases. Furthermore, since the current is continuously supplied to the memory cell 102 until the data stored in the memory cell 102 is confirmed, which may prevent some other operations from being simultaneously performed, such a structure has a limitation in improving a data processing speed.